Indentation for Verilog

Hi every body,
While programming a Verilog module, I need to press space bar for many times for proper indentation of the code, like placement of always, if-else and case statements in the hierarchy. Is there any package or shortcut key that I can use to do auto-formatting (indentation) of the code or a package that is directly indenting my code as I type?

Does tab not work?

It does, but need some auto indenting thing. Like it is sensing code and placing it at respective indent. Like in EMACS.

That’s the responsibility of the language package. If the one you’re using isn’t providing indentation help, then perhaps there’s room for improving it.